This invention relates to a data generation device for an electronic musical instrument and, more particularly, to a data generation device which can be used for generating, for example, waveform data, envelope data, tone color parameter data and other various parameter data and in which the manner of storing and reading out data is improved and an efficient utilization of a data memory is thereby realized.
The prior art concept for realizing an efficient utilization of a data memory was to adopt a compressed data representation system instead of a normal PCM system as a representation form of data stored in the data memory. U.S. Pat. No. 4,916,996, for example, discloses storage of tone waveform data which is compressed by employment of the linear prediction coding system (LPC). U.S. Pat. No. 4,809,577 also discloses waveform data compression technique.
In the prior art data storage device employing data compression as well as the conventional data storage device for the PCM system data, data is stored at each memory address at one to one relation and data length (data size, i.e., the bit number constituting single data) of data stored therein is fixed to a certain number. For example, it is normal for single data having data length of 16 bits to be stored in an address of 16 bits. As a special usage of a memory, an address of 16 bits is divided, for example, into two sections each having 8 bits and different 8-bit data are stored respectively in these memory sections. Even in this case, however, each data to be stored has fixed data length of 8 bits.
In the prior art devices in which data is stored with fixed data length, storage cells of a memory are wasted when used for data whose effective bit number is smaller than the fixed data length. In a case where, for example, tone waveform data is stored so that its maximum amplitude value may be covered with fixed data length of 16 bits, there occurs a case where the number of effective bits is only 2 bits or 3 bits at a sample point at which the amplitude value is relatively small. In such a case, storage cells of 13 bits or 14 bits for one address are undesirably wasted. The storage cells thus wasted reaches an unignorable amount when viewing the entire memory. This constitutes factor which prevents efficient utilization of a memory and, therefore, prevents realization of a compact circuit design and reduction of manufacturing cost.